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1. general description the LPC2157/2158 is a multi-chip module consisting of a lpc2138/2148 single-chip microcontroller combined with a pcf8576d universal lcd driver in a low-cost 100-pin package. the lcd driver provides 32 segments and supports from 1 to 4 backplanes. display overhead is minimized by an on-chip display ram with auto-increment addressing. refer to the respective lpc2148 and lpc2138 user manual for details. 2. features n 128-bit wide interface/accelerator enables high-speed 60 mhz operation. u 32 kb to 40 kb of on-chip static ram and 512 kb of on-chip ?ash memory. n usb 2.0 full-speed compliant device controller with 2 kb of endpoint ram. u an additional 8 kb of on-chip ram accessible to usb by dma (lpc2158 only). n 32 segment 4 backplane lcd controller supports from 1 to 4 backplanes. n single 10-bit dac provides variable analog output. n low power real-time clock (rtc) with independent power and 32 khz clock input. n multiple serial interfaces including two uarts (16c550), two fast i 2 c-bus (400 kbit/s), spi and ssp with buffering and variable data length capabilities. n single power supply chip with por and bod circuits: u cpu operating voltage range of 3.0 v to 3.6 v (3.3 v 10 %) with 5 v tolerant i/o pads. n 100-pin lqfp package with 38 microcontroller i/o pins minimum. n individual enable/disable of peripheral functions as well as peripheral clock scaling for additional power optimization. 3. ordering information LPC2157/2158 single-chip 16-bit/32-bit microcontrollers; 512 kb ?ash, with 32 segment x 4 lcd driver rev. 02 9 february 2009 product data sheet table 1. ordering information type number package name description version LPC2157fbd100 lqfp100 plastic low pro?le quad ?at package; 100 leads; body 14 14 1.4 mm sot407-1 lpc2158fbd100 lqfp100 plastic low pro?le quad ?at package; 100 leads; body 14 14 1.4 mm sot407-1
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 2 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers 4. block diagram (1) LPC2157 only. fig 1. block diagram of LPC2157/2158 a[2:0] sa0 scl, sda scl_lcd, sda_lcd osc v lcd LPC2157/ lpc2158 mcu pcf8576d lcd controller p1[31:25], p1[17:16] p0[31:28], p0[27:26] (1) , p0[25], p0[23:0] s[31:0] bp[3:0] 002aad382
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 3 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers (1) pins shared with gpio. (2) usb dma controller with 8 kb of ram accessible as general purpose ram and/or dma is available in lpc2158 only. (3) LPC2157 only. fig 2. microcontroller section block diagram 002aad384 system clock trst (1) tms (1) tck (1) tdi (1) tdo (1) xtal2 xtal1 amba ahb (advanced high-performance bus) internal flash controller ahb bridge emulation trace module test/debug interface ahb decoder ahb to apb bridge apb divider vectored interrupt controller system functions pll0 usb clock pll1 system control 512 kb flash arm7tdmi-s LPC2157/2158 internal sram controller 32 kb sram arm7 local bus apb (advanced peripheral bus) scl0, scl1 sda0, sda1 4 cap0 4 cap1 8 mat0 8 mat1 i 2 c-bus serial interfaces 0 and 1 capture/compare (w/external clock) timer 0/timer 1 eint3 to eint0 external interrupts d+ d - up_led connect vbus usb 2.0 full-speed device controller with dma (2) sck0, sck1 mosi0, mosi1 miso0, miso1 ad0[7:6], ad0[5] (3) ad0[0] (3) ad0[4:1] ad1[7:0] ssel0, ssel1 spi and ssp serial interfaces a/d converters 0 and 1 txd0, txd1 rxd0, rxd1 dsr1,cts1, rts1, dtr1, dcd1,ri1 aout uart0/uart1 d/a converter p0[31:28] and p0[25:0] p1[31:16] rtcx2 rtcx1 v bat real-time clock general purpose i/o pwm[6:1] watchdog timer pwm0 p1[31:25], p1[17:16] p0[31:28], p0[27:26] (3) p0[25], p0[23:0] fast general purpose i/o 8 kb ram shared with usb dma (2) reset
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 4 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers 5. pinning information 5.1 pinning fig 3. lcd display controller block diagram 002aad449 lcd voltage selector backplane outputs input bank selector power- on reset display ram 40 4 bits output bank selector sub- address counter data pointer blinker timing oscillator display controller command decoder i 2 c-bus controller input filters display segment outputs lcd bias generator bp0 a0 a1 a2 bp1 bp2 bp3 s[31:0] display latch shift register sa0 sda_lcd scl_lcd osc sync clk v ss v dd(lcd) v lcd fig 4. pin con?guration for LPC2157 LPC2157fbd 75 26 50 100 76 51 1 25 002aad385
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 5 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers 5.2 pin description fig 5. pin con?guration for lpc2158 lpc2158fbd 75 26 50 100 76 51 1 25 002aad444 table 2. pin description LPC2157 symbol pin type description p0[0] to p0[31] i/o port 0: port 0 is a 32-bit i/o port with individual direction controls for each bit. total of 31 pins of the port 0 can be used as a general purpose bidirectional digital i/os while p0[31] is output only pin. the operation of port 0 pins depends upon the pin function selected via the pin connect block. pin p0[24] is not available. p0[0]/txd0/ pwm1 7 [1] i/o p0[0] general purpose input/output digital pin (gpio). o txd0 transmitter output for uart0. o pwm1 pulse width modulator output 1. p0[1]/rxd0/ pwm3/eint0 9 [2] i/o p0[1] general purpose input/output digital pin (gpio). i rxd0 receiver input for uart0. o pwm3 pulse width modulator output 3. i eint0 external interrupt 0 input. p0[2]/scl0/ cap0[0] 10 [3] i/o p0[2] general purpose input/output digital pin (gpio). i/o scl0 i 2 c0 clock input/output. open-drain output (for i 2 c-bus compliance). i cap0[0] capture input for timer 0, channel 0. p0[3]/sda0/ mat0[0]/eint1 14 [3] i/o p0[3] general purpose input/output digital pin (gpio). i/o sda0 i 2 c0 data input/output. open-drain output (for i 2 c-bus compliance). o mat0[0] match output for timer 0, channel 0. i eint1 external interrupt 1 input. p0[4]/sck0/ cap0[1]/ad0[6] 15 [4] i/o p0[4] general purpose input/output digital pin (gpio). i/o sck0 serial clock for spi0. spi clock output from master or input to slave. i cap0[1] capture input for timer 0, channel 1. i ad0[6] adc 0, input 6. p0[5]/miso0/ mat0[1]/ad0[7] 17 [4] i/o p0[5] general purpose input/output digital pin (gpio). i/o miso0 master in slave out for spi0. data input to spi master or data output from spi slave. o mat0[1] match output for timer 0, channel 1. i ad0[7] adc 0, input 7.
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 6 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers p0[6]/mosi0/ cap0[2]/ad1[0] 18 [4] i/o p0[6] general purpose input/output digital pin (gpio). i/o mosi0 master out slave in for spi0. data output from spi master or data input to spi slave. i cap0[2] capture input for timer 0, channel 2. i ad1[0] adc 1, input 0. p0[7]/ssel0/ pwm2/eint2 19 [2] i/o p0[7] general purpose input/output digital pin (gpio). i ssel0 slave select for spi0. selects the spi interface as a slave. o pwm2 pulse width modulator output 2. i eint2 external interrupt 2 input. p0[8]/txd1/ pwm4/ad1[1] 20 [4] i/o p0[8] general purpose input/output digital pin (gpio). o txd1 transmitter output for uart1. o pwm4 pulse width modulator output 4. i ad1[1] adc 1, input 1. p0[9]/rxd1/ pwm6/eint3 21 [2] i/o p0[9] general purpose input/output digital pin (gpio). i rxd1 receiver input for uart1. o pwm6 pulse width modulator output 6. i eint3 external interrupt 3 input. p0[10]/rts1/ cap1[0]/ad1[2] 22 [4] i/o p0[10] general purpose input/output digital pin (gpio). o rts1 request to send output for uart1. i cap1[0] capture input for timer 1, channel 0. i ad1[2] adc 1, input 2. p0[11]/cts1/ cap1[1]/scl1 23 [3] i/o p0[11] general purpose input/output digital pin (gpio). i cts1 clear to send input for uart1. i cap1[1] capture input for timer 1, channel 1. i/o scl1 i 2 c1 clock input/output. open-drain output (for i 2 c-bus compliance) p0[12]/dsr1/ mat1[0]/ad1[3] 24 [4] i/o p0[12] general purpose input/output digital pin (gpio). i dsr1 data set ready input for uart1. o mat1[0] match output for timer 1, channel 0. i ad1[3] adc 1 input 3. p0[13]/dtr1/ mat1[1]/ad1[4] 25 [4] i/o p0[13] general purpose input/output digital pin (gpio). o dtr1 data terminal ready output for uart1. o mat1[1] match output for timer 1, channel 1. i ad1[4] adc 1 input 4. p0[14]/dcd1/ eint1/sda1 26 [3] i/o p0[14] general purpose input/output digital pin (gpio). i dcd1 data carrier detect input for uart1. i eint1 external interrupt 1 input. i/o sda1 i 2 c1 data input/output. open-drain output (for i 2 c-bus compliance). note: low on this pin while reset is low forces on-chip bootloader to take over control of the part after reset. table 2. pin description LPC2157 continued symbol pin type description
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 7 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers p0[15]/ri1/ eint2/ad1[5] 28 [4] i/o p0[15] general purpose input/output digital pin (gpio). i ri1 ring indicator input for uart1. i eint2 external interrupt 2 input. i ad1[5] adc 1, input 5. p0[16]/eint0/ mat0[2]/cap0[2] 29 [2] i/o p0[16] general purpose input/output digital pin (gpio). i eint0 external interrupt 0 input. o mat0[2] match output for timer 0, channel 2. i cap0[2] capture input for timer 0, channel 2. p0[17]/cap1[2]/ sck1/mat1[2] 30 [1] i/o p0[17] general purpose input/output digital pin (gpio). i cap1[2] capture input for timer 1, channel 2. i/o sck1 serial clock for ssp. clock output from master or input to slave. o mat1[2] match output for timer 1, channel 2. p0[18]/cap1[3]/ miso1/mat1[3] 79 [1] i/o p0[18] general purpose input/output digital pin (gpio). i cap1[3] capture input for timer 1, channel 3. i/o miso1 master in slave out for ssp. data input to spi master or data output from ssp slave. o mat1[3] match output for timer 1, channel 3. p0[19]/mat1[2]/ mosi1/cap1[2] 80 [1] i/o p0[19] general purpose input/output digital pin (gpio). o mat1[2] match output for timer 1, channel 2. i/o mosi1 master out slave in for ssp. data output from ssp master or data input to ssp slave. i cap1[2] capture input for timer 1, channel 2. p0[20]/mat1[3]/ ssel1/eint3 81 [2] i/o p0[20] general purpose input/output digital pin (gpio). o mat1[3] match output for timer 1, channel 3. i ssel1 slave select for ssp. selects the ssp interface as a slave. i eint3 external interrupt 3 input. p0[21]/pwm5/ ad1[6]/cap1[3] 91 [4] i/o p0[21] general purpose input/output digital pin (gpio). o pwm5 pulse width modulator output 5. i ad1[6] adc 1, input 6. i cap1[3] capture input for timer 1, channel 3. p0[22]/ad1[7]/ cap0[0]/ mat0[0] 92 [4] i/o p0[22] general purpose input/output digital pin (gpio). i ad1[7] adc 1, input 7. i cap0[0] capture input for timer 0, channel 0. o mat0[0] match output for timer 0, channel 0. p0[23] 84 [1] i/o p0[23] general purpose input/output digital pin (gpio). p0[25]/ad0[4]/ aout 97 [5] i/o p0[25] general purpose input/output digital pin (gpio). i ad0[4] adc 0, input 4. o aout dac output. p0[26]/ad0[5] 98 [7] i/o p0[26] general purpose input/output digital pin (gpio). i ad0[5] adc 0, input 5. this analog input is always connected to its pin. table 2. pin description LPC2157 continued symbol pin type description
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 8 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers p0[27]/ad0[0]/ cap0[1]/mat0[1] 99 [7] i/o p0[27] general purpose input/output digital pin (gpio). i ad0[0] adc 0, input 0. this analog input is always connected to its pin. i cap0[1] capture input for timer 0, channel 1. o mat0[1] match output for timer 0, channel 1. p0[28]/ad0[1]/ cap0[2]/mat0[2] 1 [4] i/o p0[28] general purpose input/output digital pin (gpio). i ad0[1] adc 0, input 1. i cap0[2] capture input for timer 0, channel 2. o mat0[2] match output for timer 0, channel 2. p0[29]/ad0[2]/ cap0[3]mat0[3] 2 [4] i/o p0[29] general purpose input/output digital pin (gpio). i ad0[2] adc 0, input 2. i cap0[3] capture input for timer 0, channel 3. o mat0[3] match output for timer 0, channel 3. p0[30]/ad0[3]/ eint3/cap0[0] 3 [4] i/o p0[30] general purpose input/output digital pin (gpio). i ad0[3] adc 0, input 3. i eint3 external interrupt 3 input. i cap0[0] capture input for timer 0, channel 0. p0[31] 5 [6] o p0[31] general purpose output only digital pin. p1[0] to p1[31] i/o port 1: port 1 is a 32-bit bidirectional i/o port with individual direction controls for each bit. the operation of port 1 pins depends upon the pin function selected via the pin connect block. pins 0 through 15 and 18 through 24 of port 1 are not available. p1[16] 4 [6] i/o p1[16] general purpose input/output digital pin (gpio). p1[17] 100 [6] i/o p1[17] general purpose input/output digital pin (gpio). p1[25]/extin0 16 [6] i/o p1[25] general purpose input/output digital pin (gpio). i extin0 external trigger input. standard i/o with internal pull-up. p1[26]/rtck 12 [6] i/o p1[26] general purpose input/output digital pin (gpio). i/o rtck returned test clock output. extra signal added to the jtag port. assists debugger synchronization when processor frequency varies. bidirectional pin with internal pull-up. note: low on rtck while reset is low enables pins p1[31:26] to operate as debug port after reset. p1[27]/tdo 90 [6] i/o p1[27] general purpose input/output digital pin (gpio). o tdo test data out for jtag interface. p1[28]/tdi 86 [6] i/o p1[28] general purpose input/output digital pin (gpio). i tdi test data in for jtag interface. p1[29]/tck 82 [6] i/o p1[29] general purpose input/output digital pin (gpio). i tck test clock for jtag interface. this clock must be slower than 1 6 of the cpu clock (cclk) for the jtag interface to operate. p1[30]/tms 78 [6] i/o p1[30] general purpose input/output digital pin (gpio). i tms test mode select for jtag interface. p1[31]/ trst 8 [6] i/o p1[31] general purpose input/output digital pin (gpio). i trst test reset for jtag interface. table 2. pin description LPC2157 continued symbol pin type description
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 9 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers [1] 5 v tolerant pad providing digital i/o functions with ttl levels and hysteresis and 10 ns slew rate control. [2] 5 v tolerant pad providing digital i/o functions with ttl levels and hysteresis and 10 ns slew rate control. if con?gured for an input function, this pad utilizes built-in glitch ?lter that blocks pulses shorter than 3 ns. [3] open-drain 5 v tolerant digital i/o i 2 c-bus 400 khz speci?cation compatible pad. it requires external pull-up to provide an output functionality. [4] 5 v tolerant pad providing digital i/o (with ttl levels and hysteresis and 10 ns slew rate control) and analog input function. if con?gured for an input function, this pad utilizes built-in glitch ?lter that blocks pulses shorter than 3 ns. when con?gured as an adc i nput, digital section of the pad is disabled. [5] 5 v tolerant pad providing digital i/o (with ttl levels and hysteresis and 10 ns slew rate control) and analog output function . when con?gured as the dac output, digital section of the pad is disabled. [6] 5 v tolerant pad with built-in pull-up resistor providing digital i/o functions with ttl levels and hysteresis and 10 ns slew rate control. the pull-up resistors value typically ranges from 60 k w to 300 k w . [7] pad is designed in accordance with the universal serial bus (usb) speci?cation, revision 2.0 (full-speed and low-speed mode only). [8] 5 v tolerant pad providing digital input (with ttl levels and hysteresis) function only. [9] pad provides special analog functionality. reset 83 [8] i external reset input: a low on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at address 0. ttl with hysteresis, 5 v tolerant. xtal1 88 [9] o input from the oscillator ampli?er. xtal2 87 [9] i output to the oscillator circuit and internal clock generator circuits. rtcx1 93 [9] i input to the rtc oscillator circuit. rtcx2 94 [9] o output from the rtc oscillator circuit. v ss 6, 13, 32, 39, 40, 85, 95 i ground: 0 v reference. v dd 11, 27, 33 i 3.3 v power supply: this is the power supply voltage for the core and i/o ports. v dda 96 i analog 3.3 v power supply: this should be nominally the same voltage as v dd but should be isolated to minimize noise and error. this voltage is only used to power the on-chip adc(s) and dac. v dd(lcd) 38 i 1.8 v to 5.5 v power supply: power supply voltage for the pcf8576d. v lcd 41 i lcd power supply: lcd voltage. vref 89 i adc reference voltage: this should be nominally less than or equal to the v dd voltage but should be isolated to minimize noise and error. level on this pin is used as a reference for adc(s) and dac. vbat 31 i rtc power supply voltage: 3.3 v on this pin supplies the power to the rtc. sda_lcd 34 i/o sda lcd i 2 c-bus data signal for the lcd controller. scl_lcd 35 i scl lcd i 2 c-bus clock signal for the lcd controller. sync 36 i/o sync cascade synchronization input/output clk 37 i/o clk external clock input/output bp0 to bp3 42 to 45 o bp0 to bp3: lcd backplane outputs. s0 to s31 46 to 77 o s0 to s31: lcd segment outputs. table 2. pin description LPC2157 continued symbol pin type description
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 10 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers table 3. pin description lpc2158 symbol pin type description p0[0] to p0[31] i/o port 0: port 0 is a 32-bit i/o port with individual direction controls for each bit. total of 29 pins of the port 0 can be used as a general purpose bidirectional digital i/os while p0[31] is output only pin. the operation of port 0 pins depends upon the pin function selected via the pin connect block. pins p0[24], p0[26] and p0[27] are not available. p0[0]/txd0/ pwm1 7 [1] i/o p0[0] general purpose input/output digital pin (gpio). o txd0 transmitter output for uart0. o pwm1 pulse width modulator output 1. p0[1]/rxd0/ pwm3/eint0 9 [2] i/o p0[1] general purpose input/output digital pin (gpio). i rxd0 receiver input for uart0. o pwm3 pulse width modulator output 3. i eint0 external interrupt 0 input. p0[2]/scl0/ cap0[0] 10 [3] i/o p0[2] general purpose input/output digital pin (gpio). i/o scl0 i 2 c0 clock input/output. open-drain output (for i 2 c-bus compliance). i cap0[0] capture input for timer 0, channel 0. p0[3]/sda0/ mat0[0]/eint1 14 [3] i/o p0[3] general purpose input/output digital pin (gpio). i/o sda0 i 2 c0 data input/output. open-drain output (for i 2 c-bus compliance). o mat0[0] match output for timer 0, channel 0. i eint1 external interrupt 1 input. p0[4]/sck0/ cap0[1]/ad0[6] 15 [4] i/o p0[4] general purpose input/output digital pin (gpio). i/o sck0 serial clock for spi0. spi clock output from master or input to slave. i cap0[1] capture input for timer 0, channel 1. i ad0[6] adc 0, input 6. p0[5]/miso0/ mat0[1]/ad0[7] 17 [4] i/o p0[5] general purpose input/output digital pin (gpio). i/o miso0 master in slave out for spi0. data input to spi master or data output from spi slave. o mat0[1] match output for timer 0, channel 1. i ad0[7] adc 0, input 7. p0[6]/mosi0/ cap0[2]/ad1[0] 18 [4] i/o p0[6] general purpose input/output digital pin (gpio). i/o mosi0 master out slave in for spi0. data output from spi master or data input to spi slave. i cap0[2] capture input for timer 0, channel 2. i ad1[0] adc 1, input 0. p0[7]/ssel0/ pwm2/eint2 19 [2] i/o p0[7] general purpose input/output digital pin (gpio). i ssel0 slave select for spi0. selects the spi interface as a slave. o pwm2 pulse width modulator output 2. i eint2 external interrupt 2 input. p0[8]/txd1/ pwm4/ad1[1] 20 [4] i/o p0[8] general purpose input/output digital pin (gpio). o txd1 transmitter output for uart1. o pwm4 pulse width modulator output 4. i ad1[1] adc 1, input 1.
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 11 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers p0[9]/rxd1/ pwm6/eint3 21 [2] i/o p0[9] general purpose input/output digital pin (gpio). i rxd1 receiver input for uart1. o pwm6 pulse width modulator output 6. i eint3 external interrupt 3 input. p0[10]/rts1/ cap1[0]/ad1[2] 22 [4] i/o p0[10] general purpose input/output digital pin (gpio). o rts1 request to send output for uart1. i cap1[0] capture input for timer 1, channel 0. i ad1[2] adc 1, input 2. p0[11]/cts1/ cap1[1]/scl1 23 [3] i/o p0[11] general purpose input/output digital pin (gpio). i cts1 clear to send input for uart1. i cap1[1] capture input for timer 1, channel 1. i/o scl1 i 2 c1 clock input/output. open-drain output (for i 2 c-bus compliance) p0[12]/dsr1/ mat1[0]/ad1[3] 24 [4] i/o p0[12] general purpose input/output digital pin (gpio). i dsr1 data set ready input for uart1. o mat1[0] match output for timer 1, channel 0. i ad1[3] adc 1 input 3. p0[13]/dtr1/ mat1[1]/ad1[4] 25 [4] i/o p0[13] general purpose input/output digital pin (gpio). o dtr1 data terminal ready output for uart1. o mat1[1] match output for timer 1, channel 1. i ad1[4] adc 1 input 4. p0[14]/dcd1/ eint1/sda1 26 [3] i/o p0[14] general purpose input/output digital pin (gpio). i dcd1 data carrier detect input for uart1. i eint1 external interrupt 1 input. i/o sda1 i 2 c1 data input/output. open-drain output (for i 2 c-bus compliance). note: low on this pin while reset is low forces on-chip bootloader to take over control of the part after reset. p0[15]/ri1/ eint2/ad1[5] 28 [4] i/o p0[15] general purpose input/output digital pin (gpio). i ri1 ring indicator input for uart1. i eint2 external interrupt 2 input. i ad1[5] adc 1, input 5. p0[16]/eint0/ mat0[2]/cap0[2] 29 [2] i/o p0[16] general purpose input/output digital pin (gpio). i eint0 external interrupt 0 input. o mat0[2] match output for timer 0, channel 2. i cap0[2] capture input for timer 0, channel 2. p0[17]/cap1[2]/ sck1/mat1[2] 30 [1] i/o p0[17] general purpose input/output digital pin (gpio). i cap1[2] capture input for timer 1, channel 2. i/o sck1 serial clock for ssp. clock output from master or input to slave. o mat1[2] match output for timer 1, channel 2. table 3. pin description lpc2158 continued symbol pin type description
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 12 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers p0[18]/cap1[3]/ miso1/mat1[3] 79 [1] i/o p0[18] general purpose input/output digital pin (gpio). i cap1[3] capture input for timer 1, channel 3. i/o miso1 master in slave out for ssp. data input to spi master or data output from ssp slave. o mat1[3] match output for timer 1, channel 3. p0[19]/mat1[2]/ mosi1/cap1[2] 80 [1] i/o p0[19] general purpose input/output digital pin (gpio). o mat1[2] match output for timer 1, channel 2. i/o mosi1 master out slave in for ssp. data output from ssp master or data input to ssp slave. i cap1[2] capture input for timer 1, channel 2. p0[20]/mat1[3]/ ssel1/eint3 81 [2] i/o p0[20] general purpose input/output digital pin (gpio). o mat1[3] match output for timer 1, channel 3. i ssel1 slave select for ssp. selects the ssp interface as a slave. i eint3 external interrupt 3 input. p0[21]/pwm5/ ad1[6]/cap1[3] 91 [4] i/o p0[21] general purpose input/output digital pin (gpio). o pwm5 pulse width modulator output 5. i ad1[6] adc 1, input 6. i cap1[3] capture input for timer 1, channel 3. p0[22]/ad1[7]/ cap0[0]/ mat0[0] 92 [4] i/o p0[22] general purpose input/output digital pin (gpio). i ad1[7] adc 1, input 7. i cap0[0] capture input for timer 0, channel 0. o mat0[0] match output for timer 0, channel 0. p0[23]/v bus 84 [1] i/o p0[23] general purpose input/output digital pin (gpio). i v bus indicates the presence of usb bus power. note: this signal must be high for usb reset to occur. p0[25]/ad0[4]/ aout 97 [5] i/o p0[25] general purpose input/output digital pin (gpio). i ad0[4] adc 0, input 4. o aout dac output. p0[28]/ad0[1]/ cap0[2]/mat0[2] 1 [4] i/o p0[28] general purpose input/output digital pin (gpio). i ad0[1] adc 0, input 1. i cap0[2] capture input for timer 0, channel 2. o mat0[2] match output for timer 0, channel 2. p0[29]/ad0[2]/ cap0[3]/mat0[3] 2 [4] i/o p0[29] general purpose input/output digital pin (gpio). i ad0[2] adc 0, input 2. i cap0[3] capture input for timer 0, channel 3. o mat0[3] match output for timer 0, channel 3. p0[30]/ad0[3]/ eint3/cap0[0] 3 [4] i/o p0[30] general purpose input/output digital pin (gpio). i ad0[3] adc 0, input 3. i eint3 external interrupt 3 input. i cap0[0] capture input for timer 0, channel 0. table 3. pin description lpc2158 continued symbol pin type description
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 13 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers p0[31]/up_led/ connect 5 [6] o p0[31] general purpose output only digital pin. o up_led usb goodlink led indicator. it is low when device is con?gured (non-control endpoints enabled). it is high when the device is not con?gured or during global suspend. o connect signal used to switch an external 1.5 k w resistor under the software control. used with the softconnect usb feature. important: this is an digital output only pin. this pin must not be externally pulled low when reset pin is low or the jtag port will be disabled. p1[0] to p1[31] i/o port 1: port 1 is a 32-bit bidirectional i/o port with individual direction controls for each bit. the operation of port 1 pins depends upon the pin function selected via the pin connect block. pins 0 through 15 and 18 through 24 of port 1 are not available. p1[16] 4 [6] i/o p1[16] general purpose input/output digital pin (gpio). p1[17] 100 [6] i/o p1[17] general purpose input/output digital pin (gpio). p1[25]/extin0 16 [6] i/o p1[25] general purpose input/output digital pin (gpio). i extin0 external trigger input. standard i/o with internal pull-up. p1[26]/rtck 12 [6] i/o p1[26] general purpose input/output digital pin (gpio). i/o rtck returned test clock output. extra signal added to the jtag port. assists debugger synchronization when processor frequency varies. bidirectional pin with internal pull-up. note: low on rtck while reset is low enables pins p1[31:26] to operate as debug port after reset. p1[27]/tdo 90 [6] i/o p1[27] general purpose input/output digital pin (gpio). o tdo test data out for jtag interface. p1[28]/tdi 86 [6] i/o p1[28] general purpose input/output digital pin (gpio). i tdi test data in for jtag interface. p1[29]/tck 82 [6] i/o p1[29] general purpose input/output digital pin (gpio). i tck test clock for jtag interface. this clock must be slower than 1 6 of the cpu clock (cclk) for the jtag interface to operate. p1[30]/tms 78 [6] i/o p1[30] general purpose input/output digital pin (gpio). i tms test mode select for jtag interface. p1[31]/ trst 8 [6] i/o p1[31] general purpose input/output digital pin (gpio). i trst test reset for jtag interface. d+ 98 [7] i/o usb bidirectional d+ line. d - 99 [7] i/o usb bidirectional d - line. reset 83 [8] i external reset input: a low on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at address 0. ttl with hysteresis, 5 v tolerant. xtal1 88 [9] o input from the oscillator ampli?er. xtal2 87 [9] i output to the oscillator circuit and internal clock generator circuits. rtcx1 93 [9] i input to the rtc oscillator circuit. rtcx2 94 [9] o output from the rtc oscillator circuit. v ss 6, 13, 32, 39, 40, 85, 95 i ground: 0 v reference. table 3. pin description lpc2158 continued symbol pin type description
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 14 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers [1] 5 v tolerant pad providing digital i/o functions with ttl levels and hysteresis and 10 ns slew rate control. [2] 5 v tolerant pad providing digital i/o functions with ttl levels and hysteresis and 10 ns slew rate control. if con?gured for an input function, this pad utilizes built-in glitch ?lter that blocks pulses shorter than 3 ns. [3] open-drain 5 v tolerant digital i/o i 2 c-bus 400 khz speci?cation compatible pad. it requires external pull-up to provide an output functionality. [4] 5 v tolerant pad providing digital i/o (with ttl levels and hysteresis and 10 ns slew rate control) and analog input function. if con?gured for an input function, this pad utilizes built-in glitch ?lter that blocks pulses shorter than 3 ns. when con?gured as an adc i nput, digital section of the pad is disabled. [5] 5 v tolerant pad providing digital i/o (with ttl levels and hysteresis and 10 ns slew rate control) and analog output function . when con?gured as the dac output, digital section of the pad is disabled. [6] 5 v tolerant pad with built-in pull-up resistor providing digital i/o functions with ttl levels and hysteresis and 10 ns slew rate control. the pull-up resistors value typically ranges from 60 k w to 300 k w . [7] pad is designed in accordance with the universal serial bus (usb) speci?cation, revision 2.0 (full-speed and low-speed mode only). [8] 5 v tolerant pad providing digital input (with ttl levels and hysteresis) function only. [9] pad provides special analog functionality. v dd 11, 27, 33 i 3.3 v power supply: this is the power supply voltage for the core and i/o ports. v dda 96 i analog 3.3 v power supply: this should be nominally the same voltage as v dd but should be isolated to minimize noise and error. this voltage is only used to power the on-chip adc(s) and dac. v dd(lcd) 38 i 1.8 v to 5.5 v power supply: power supply voltage for the pcf8576d. v lcd 41 i lcd power supply: lcd voltage. vref 89 i adc reference voltage: this should be nominally less than or equal to the v dd voltage but should be isolated to minimize noise and error. level on this pin is used as a reference for adc(s) and dac. vbat 31 i rtc power supply voltage: 3.3 v on this pin supplies the power to the rtc. sda_lcd 34 i/o sda lcd i 2 c-bus data signal for the lcd controller. scl_lcd 35 i scl lcd i 2 c-bus clock signal for the lcd controller. sync 36 i/o sync cascade synchronization input/output clk 37 i/o clk external clock input/output bp0 to bp3 42 to 45 o bp0 to bp3: lcd backplane outputs. s0 to s31 46 to 77 o s0 to s31: lcd segment outputs. table 3. pin description lpc2158 continued symbol pin type description
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 15 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers 6. functional description 6.1 architectural overview the arm7tdmi-s is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. the arm architecture is based on reduced instruction set computer (risc) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed complex instruction set computers (cisc). this simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core. pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. the arm7tdmi-s processor also employs a unique architectural strategy known as thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. the key idea behind thumb is that of a super-reduced instruction set. essentially, the arm7tdmi-s processor has two instruction sets: ? the standard 32-bit arm set. ? a 16-bit thumb set. the thumb sets 16-bit instruction length allows it to approach twice the density of standard arm code while retaining most of the arms performance advantage over a traditional 16-bit processor using 16-bit registers. this is possible because thumb code operates on the same 32-bit register set as arm code. thumb code is able to provide up to 65 % of the code size of arm, and 160 % of the performance of an equivalent arm processor connected to a 16-bit memory system. 6.2 on-chip ?ash program memory the LPC2157/2158 incorporate a 512 kb ?ash memory system. this memory may be used for both code and data storage. programming of the ?ash memory may be accomplished in several ways. it may be programmed in system via the serial port. the application program may also erase and/or program the ?ash while the application is running, allowing a great degree of ?exibility for data storage ?eld ?rmware upgrades, etc. due to the architectural solution chosen for an on-chip bootloader, ?ash memory available for users code on LPC2157/2158 is 500 kb respectively. the LPC2157/2158 ?ash memory provides a minimum of 400000 erase/write cycles and 20 years of data-retention. 6.3 on-chip static ram on-chip static ram may be used for code and/or data storage. the sram may be accessed as 8-bit, 16-bit, and 32-bit. the LPC2157/2158 provide 32 kb and 40 kb of static ram.
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 16 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers in case of lpc2158 only, an 8 kb sram block intended to be utilized mainly by the usb can also be used as a general purpose ram for data storage and code storage and execution. 6.4 memory map the LPC2157/2158 memory map incorporates several distinct regions, as shown in figure 6 . in addition, the cpu interrupt vectors may be remapped to allow them to reside in either ?ash memory (the default) or on-chip static ram. this is described in section 6.19 system control . 6.5 interrupt controller the vectored interrupt controller (vic) accepts all of the interrupt request inputs and categorizes them as fast interrupt request (fiq), vectored interrupt request (irq), and non-vectored irq as de?ned by programmable settings. the programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted. fig 6. LPC2157/2158 memory map ahb peripherals apb peripherals reserved address space reserved address space boot block (re-mapped from on-chip flash memory reserved address space 32 kb on-chip static ram (LPC2157/2158) 512 kb on-chip non-volatile memory (LPC2157/2158) 0xffff ffff 0xf000 0000 0xe000 0000 0xc000 0000 0x8000 0000 0x7fff ffff 0x4000 4000 0x4001 8000 0x4000 7fff 0x7fff d000 0x7fff cfff 0x0008 0000 0x0007 ffff 0x0001 0000 4.0 gb 3.75 gb 3.5 gb 3.0 gb 2.0 gb 1.0 gb 0.0 gb 002aad402
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 17 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers fiq has the highest priority. if more than one request is assigned to fiq, the vic combines the requests to produce the fiq signal to the arm processor. the fastest possible fiq latency is achieved when only one request is classi?ed as fiq, because then the fiq service routine does not need to branch into the interrupt service routine but can run from the interrupt vector location. if more than one request is assigned to the fiq class, the fiq service routine will read a word from the vic that identi?es which fiq source(s) is (are) requesting an interrupt. vectored irqs have the middle priority. sixteen of the interrupt requests can be assigned to this category. any of the interrupt requests can be assigned to any of the 16 vectored irq slots, among which slot 0 has the highest priority and slot 15 has the lowest. non-vectored irqs have the lowest priority. the vic combines the requests from all the vectored and non-vectored irqs to produce the irq signal to the arm processor. the irq service routine can start by reading a register from the vic and jumping there. if any of the vectored irqs are pending, the vic provides the address of the highest-priority requesting irqs service routine, otherwise it provides the address of a default routine that is shared by all the non-vectored irqs. the default routine can read another vic register to see what irqs are active. 6.5.1 interrupt sources each peripheral device has one interrupt line connected to the vectored interrupt controller, but may have several internal interrupt ?ags. individual interrupt ?ags may also represent more than one interrupt source. 6.6 pin connect block the pin connect block allows selected pins of the microcontroller to have more than one function. con?guration registers control the multiplexers to allow connection between the pin and the on chip peripherals. peripherals should be connected to the appropriate pins prior to being activated, and prior to any related interrupt(s) being enabled. activity of any enabled peripheral function that is not mapped to a related pin should be considered unde?ned. the pin control module with its pin select registers de?nes the functionality of the microcontroller in a given hardware environment. after reset all pins of port 0 and port 1 are con?gured as input with the following exceptions: if debug is enabled, the jtag pins will assume their jtag functionality. the pins associated with the i 2 c0 and i 2 c1 interface are open drain. 6.7 fast general purpose parallel i/o device pins that are not connected to a speci?c peripheral function are controlled by the gpio registers. pins may be dynamically con?gured as inputs or outputs. separate registers allow setting or clearing any number of outputs simultaneously. the value of the output register may be read back, as well as the current state of the port pins. LPC2157/2158 introduce accelerated gpio functions over prior lpc2000 devices: ? gpio registers are relocated to the arm local bus for the fastest possible i/o timing.
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 18 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers ? mask registers allow treating sets of port bits as a group, leaving other bits unchanged. ? all gpio registers are byte addressable. ? entire port value can be written in one instruction. 6.7.1 features ? bit-level set and clear registers allow a single instruction set or clear of any number of bits in one port. ? direction control of individual bits. ? separate control of output set and clear. ? all i/o default to inputs after reset. 6.8 10-bit adc the LPC2157/2158 contain two single 10-bit successive approximation adcs. while adc0 has eight channels (six channels for lpc2158), adc1 has eight channels. therefore, the total number of available adc inputs for LPC2157 is 16 and for lpc2158 is 14. 6.8.1 features ? 10-bit successive approximation adc. ? measurement range of 0 v to vref (2.0 v vref v dda ). ? each converter capable of performing more than 400000 10-bit samples per second. ? every analog input has a dedicated result register to reduce interrupt overhead. ? burst conversion mode for single or multiple inputs. ? optional conversion on transition on input pin or timer match signal. ? global start command for both converters. 6.9 10-bit dac the dac enables the LPC2157/2158 to generate a variable analog output. the maximum dac output voltage is the vref voltage. 6.9.1 features ? 10-bit dac. ? buffered output. ? power-down mode available. ? selectable speed versus power. 6.10 usb 2.0 device controller (lpc2158 only) the usb is a 4-wire serial bus that supports communication between a host and a number (127 max) of peripherals. the host controller allocates the usb bandwidth to attached devices through a token based protocol. the bus supports hot plugging, unplugging, and dynamic con?guration of the devices. all transactions are initiated by the host controller.
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 19 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers the lpc2158 is equipped with a usb device controller that enables 12 mbit/s data exchange with a usb host controller. it consists of a register interface, serial interface engine, endpoint buffer memory and dma controller. the serial interface engine decodes the usb data stream and writes data to the appropriate end point buffer memory. the status of a completed usb transfer or error condition is indicated via status registers. an interrupt is also generated if enabled. a dma controller can transfer data between an endpoint buffer and the usb ram. 6.10.1 features ? fully compliant with usb 2.0 full-speed speci?cation. ? supports 32 physical (16 logical) endpoints. ? supports control, bulk, interrupt and isochronous endpoints. ? scalable realization of endpoints at run time. ? endpoint maximum packet size selection (up to usb maximum speci?cation) by software at run time. ? ram message buffer size based on endpoint realization and maximum packet size. ? supports softconnect and goodlink led indicator. these two functions are sharing one pin. ? supports bus-powered capability with low suspend current. ? supports dma transfer on all non-control endpoints. ? one duplex dma channel serves all endpoints. ? allows dynamic switching between cpu controlled and dma modes. ? double buffer implementation for bulk and isochronous endpoints. 6.11 uarts the LPC2157/2158 each contain two uarts. in addition to standard transmit and receive data lines, the uart1 also provides a full modem control handshake interface. compared to previous lpc2000 microcontrollers, uarts in LPC2157/2158 introduce a fractional baud rate generator for both uarts, enabling these microcontrollers to achieve standard baud rates such as 115200 bd with any crystal frequency above 2 mhz. in addition, auto-cts/rts ?ow-control functions are fully implemented in hardware. 6.11.1 features ? 16 b receive and transmit fifos. ? register locations conform to 16c550 industry standard. ? receiver fifo trigger points at 1 b, 4 b, 8 b and 14 b ? built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. ? transmission fifo control enables implementation of software (xon/xoff) ?ow control on both uarts. ? lpc2158 uart1 equipped with standard modem interface signals. this module also provides full support for hardware ?ow control (auto-cts/rts).
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 20 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers 6.12 i 2 c-bus serial i/o controller the LPC2157/2158 each contain two i 2 c-bus controllers. the i 2 c-bus is bidirectional, for inter-ic control using only two wires: a serial clock line (scl), and a serial data line (sda). each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an lcd driver or a transmitter with the capability to both receive and send information (such as memory)). transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. the i 2 c-bus is a multi-master bus, it can be controlled by more than one bus master connected to it. the i 2 c-bus implemented in LPC2157/2158 supports bit rates up to 400 kbit/s (fast i 2 c-bus). 6.12.1 features ? compliant with standard i 2 c-bus interface. ? easy to con?gure as master, slave, or master/slave. ? programmable clocks allow versatile rate control. ? bidirectional data transfer between masters and slaves. ? multi-master bus (no central master). ? arbitration between simultaneously transmitting masters without corruption of serial data on the bus. ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus. ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. ? the i 2 c-bus can be used for test and diagnostic purposes. 6.13 spi serial i/o controller the LPC2157/2158 each contain one spi controller. the spi is a full duplex serial interface, designed to handle multiple masters and slaves connected to a given bus. only a single master and a single slave can communicate on the interface during a given data transfer. during a data transfer the master always sends a byte of data to the slave, and the slave always sends a byte of data to the master. 6.13.1 features ? compliant with spi speci?cation. ? synchronous, serial, full duplex, communication. ? combined spi master and slave. ? maximum data bit rate of one eighth of the input clock rate. 6.14 ssp serial i/o controller the LPC2157/2158 each contain one serial synchronous port controller (ssp). the ssp controller is capable of operation on a spi, 4-wire ssi, or microwire bus. it can interact with multiple masters and slaves on the bus. however, only a single master and a single
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 21 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers slave can communicate on the bus during a given data transfer. the ssp supports full duplex transfers, with data frames of 4 bits to 16 bits of data ?owing from the master to the slave and from the slave to the master. often only one of these data ?ows carries meaningful data. 6.14.1 features ? compatible with motorolas spi, tis 4-wire ssi and national semiconductors microwire buses. ? synchronous serial communication. ? master or slave operation. ? 8-frame fifos for both transmit and receive. ? four bits to 16 bits per frame. 6.15 general purpose timers/external event counters the timer/counter is designed to count cycles of the peripheral clock (pclk) or an externally supplied clock and optionally generate interrupts or perform other actions at speci?ed timer values, based on four match registers. it also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. multiple pins can be selected to perform a single capture or match function, providing an application with or and and, as well as broadcast functions among them. the LPC2157/2158 can count external events on one of the capture inputs if the minimum external pulse is equal or longer than a period of the pclk. in this con?guration, unused capture lines can be selected as regular timer capture inputs, or used as external interrupts. 6.15.1 features ? a 32-bit timer/counter with a programmable 32-bit prescaler. ? external event counter or timer operation. ? four 32-bit capture channels per timer/counter that can take a snapshot of the timer value when an input signal transitions. a capture event may also optionally generate an interrupt. ? four 32-bit match registers that allow: C continuous operation with optional interrupt generation on match. C stop timer on match with optional interrupt generation. C reset timer on match with optional interrupt generation. ? four external outputs per timer/counter corresponding to match registers, with the following capabilities: C set low on match. C set high on match. C toggle on match. C do nothing on match.
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 22 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers 6.16 watchdog timer the purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. when enabled, the watchdog will generate a system reset if the user program fails to feed (or reload) the watchdog within a predetermined amount of time. 6.16.1 features ? internally resets chip if not periodically reloaded. ? debug mode. ? enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. ? incorrect/incomplete feed sequence causes reset/interrupt if enabled. ? flag to indicate watchdog reset. ? programmable 32-bit timer with internal prescaler. ? selectable time period from (t cy(pclk) 256 4) to (t cy(pclk) 2 32 4) in multiples of t cy(pclk) 4. 6.17 real-time clock the rtc is designed to provide a set of counters to measure time when normal or idle operating mode is selected. the rtc has been designed to use little power, making it suitable for battery powered systems where the cpu is not running continuously (idle mode). 6.17.1 features ? measures the passage of time to maintain a calendar and clock. ? ultra-low power design to support battery powered systems. ? provides seconds, minutes, hours, day of month, month, year, day of week, and day of year. ? can use either the rtc dedicated 32 khz oscillator input or clock derived from the external crystal/oscillator input at xtal1. programmable reference clock divider allows ?ne adjustment of the rtc. ? dedicated power supply pin can be connected to a battery or the main 3.3 v. 6.18 pulse width modulator the pwm is based on the standard timer block and inherits all of its features, although only the pwm function is pinned out on the LPC2157/2158. the timer is designed to count cycles of the peripheral clock (pclk) and optionally generate interrupts or perform other actions when speci?ed timer values occur, based on seven match registers. the pwm function is also based on match register events. the ability to separately control rising and falling edge locations allows the pwm to be used for more applications. for instance, multi-phase motor control typically requires three non-overlapping pwm outputs with individual control of all three pulse widths and positions.
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 23 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers two match registers can be used to provide a single edge controlled pwm output. one match register (mr0) controls the pwm cycle rate, by resetting the count upon match. the other match register controls the pwm edge position. additional single edge controlled pwm outputs require only one match register each, since the repetition rate is the same for all pwm outputs. multiple single edge controlled pwm outputs will all have a rising edge at the beginning of each pwm cycle, when an mr0 match occurs. three match registers can be used to provide a pwm output with both edges controlled. again, the mr0 match register controls the pwm cycle rate. the other match registers control the two pwm edge positions. additional double edge controlled pwm outputs require only two match registers each, since the repetition rate is the same for all pwm outputs. with double edge controlled pwm outputs, speci?c match registers control the rising and falling edge of the output. this allows both positive going pwm pulses (when the rising edge occurs prior to the falling edge), and negative going pwm pulses (when the falling edge occurs prior to the rising edge). 6.18.1 features ? seven match registers allow up to six single edge controlled or three double edge controlled pwm outputs, or a mix of both types. ? the match registers also allow: C continuous operation with optional interrupt generation on match. C stop timer on match with optional interrupt generation. C reset timer on match with optional interrupt generation. ? supports single edge controlled and/or double edge controlled pwm outputs. single edge controlled pwm outputs all go high at the beginning of each cycle unless the output is a constant low. double edge controlled pwm outputs can have either edge occur at any position within a cycle. this allows for both positive going and negative going pulses. ? pulse period and width can be any number of timer counts. this allows complete ?exibility in the trade-off between resolution and repetition rate. all pwm outputs will occur at the same repetition rate. ? double edge controlled pwm outputs can be programmed to be either positive going or negative going pulses. ? match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses. software must release new match values before they can become effective. ? may be used as a standard timer if the pwm mode is not enabled. ? a 32-bit timer/counter with a programmable 32-bit prescaler.
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 24 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers 6.19 system control 6.19.1 crystal oscillator on-chip integrated oscillator operates with external crystal in range of 1 mhz to 25 mhz. the oscillator output frequency is called f osc and the arm processor clock frequency is referred to as cclk for purposes of rate equations, etc. f osc and cclk are the same value unless the pll is running and connected. refer to section 6.19.2 pll for additional information. 6.19.2 pll the pll accepts an input clock frequency in the range of 10 mhz to 25 mhz. the input frequency is multiplied up into the range of 10 mhz to 60 mhz with a current controlled oscillator (cco). the multiplier can be an integer value from 1 to 32 (in practice, the multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper frequency limit of the cpu). the cco operates in the range of 156 mhz to 320 mhz, so there is an additional divider in the loop to keep the cco within its frequency range while the pll is providing the desired output frequency. the output divider may be set to divide by 2, 4, 8 or 16 to produce the output clock. since the minimum output divider value is 2, it is insured that the pll output has a 50 % duty cycle. the pll is turned off and bypassed following a chip reset and may be enabled by software. the program must con?gure and activate the pll, wait for the pll to lock, then connect to the pll as a clock source. the pll settling time is 100 m s. 6.19.3 reset and wake-up timer reset has two sources on the LPC2157/2158: the reset pin and watchdog reset. the reset pin is a schmitt trigger input pin with an additional glitch ?lter. assertion of chip reset by any source starts the wake-up timer (see wake-up timer description below), causing the internal chip reset to remain asserted until the external reset is de-asserted, the oscillator is running, a ?xed number of clocks have passed, and the on-chip ?ash controller has completed its initialization. when the internal reset is removed, the processor begins executing at address 0, which is the reset vector. at that point, all of the processor and peripheral registers have been initialized to predetermined values. the wake-up timer ensures that the oscillator and other analog functions required for chip operation are fully functional before the processor is allowed to execute instructions. this is important at power on, all types of reset, and whenever any of the aforementioned functions are turned off for any reason. since the oscillator and other functions are turned off during power-down mode, any wake-up of the processor from power-down mode makes use of the wake-up timer. the wake-up timer monitors the crystal oscillator as the means of checking whether it is safe to begin code execution. when power is applied to the chip, or some event caused the chip to exit power-down mode, some time is required for the oscillator to produce a signal of suf?cient amplitude to drive the clock logic. the amount of time depends on many factors, including the rate of v dd ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing ambient conditions.
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 25 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers 6.19.4 brownout detector the LPC2157/2158 include 2-stage monitoring of the voltage on the v dd pins. if this voltage falls below 2.9 v, the bod asserts an interrupt signal to the vic. this signal can be enabled for interrupt; if not, software can monitor the signal by reading dedicated register. the second stage of low voltage detection asserts reset to inactivate the LPC2157/2158 when the voltage on the v dd pins falls below 2.6 v. this reset prevents alteration of the ?ash as operation of the various elements of the chip would otherwise become unreliable due to low voltage. the bod circuit maintains this reset down below 1 v, at which point the por circuitry maintains the overall reset. both the 2.9 v and 2.6 v thresholds include some hysteresis. in normal operation, this hysteresis allows the 2.9 v detection to reliably interrupt, or a regularly-executed event loop to sense the condition. 6.19.5 code security this feature of the LPC2157/2158 allow an application to control whether it can be debugged or protected from observation. if after reset on-chip bootloader detects a valid checksum in ?ash and reads 0x8765 4321 from address 0x1fc in ?ash, debugging will be disabled and thus the code in ?ash will be protected from observation. once debugging is disabled, it can be enabled only by performing a full chip erase using the isp. 6.19.6 external interrupt inputs the LPC2157/2158 include up to nine edge or level sensitive external interrupt inputs as selectable pin functions. when the pins are combined, external events can be processed as four independent interrupt signals. the external interrupt inputs can optionally be used to wake-up the processor from power-down mode. additionally capture input pins can also be used as external interrupts without the option to wake the device up from power-down mode. 6.19.7 memory mapping control the memory mapping control alters the mapping of the interrupt vectors that appear beginning at address 0x0000 0000. vectors may be mapped to the bottom of the on-chip ?ash memory, or to the on-chip static ram. this allows code running in different memory spaces to have control of the interrupts. 6.19.8 power control the LPC2157/2158 supports two reduced power modes: idle mode and power-down mode. in idle mode, execution of instructions is suspended until either a reset or interrupt occurs. peripheral functions continue operation during idle mode and may generate interrupts to cause the processor to resume execution. idle mode eliminates power used by the processor itself, memory systems and related controllers, and internal buses.
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 26 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers in power-down mode, the oscillator is shut down and the chip receives no internal clocks. the processor state and registers, peripheral registers, and internal sram values are preserved throughout power-down mode and the logic levels of chip output pins remain static. the power-down mode can be terminated and normal operation resumed by either a reset or certain speci?c interrupts that are able to function without clocks. since all dynamic operation of the chip is suspended, power-down mode reduces chip power consumption to nearly zero. selecting an external 32 khz clock instead of the pclk as a clock-source for the on-chip rtc will enable the microcontroller to have the rtc active during power-down mode. power-down current is increased with rtc active. however, it is signi?cantly lower than in idle mode. a power control for peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings during active and idle mode. 6.19.9 apb bus the apb divider determines the relationship between the processor clock (cclk) and the clock used by peripheral devices (pclk). the apb divider serves two purposes. the ?rst is to provide peripherals with the desired pclk via apb bus so that they can operate at the speed chosen for the arm processor. in order to achieve this, the apb bus may be slowed down to 1 2 to 1 4 of the processor clock rate. because the apb bus must work properly at power-up (and its timing cannot be altered if it does not work since the apb divider control registers reside on the apb bus), the default condition at reset is for the apb bus to run at 1 4 of the processor clock rate. the second purpose of the apb divider is to allow power savings when an application does not require any peripherals to run at the full processor rate. because the apb divider is connected to the pll output, the pll remains active (if it was running) during idle mode. 6.20 emulation and debugging the LPC2157/2158 supports emulation and debugging via a jtag serial port. debugging functions are multiplexed with gpios on port 1. this means that all communication, timer and interface peripherals residing on port 0 are available during the development and debugging phase as they are when the application is run in the embedded system itself. 6.20.1 embeddedice standard arm embeddedice logic provides on-chip debug support. the debugging of the target system requires a host computer running the debugger software and an embeddedice protocol convertor. embeddedice protocol convertor converts the remote debug protocol commands to the jtag data needed to access the arm core. the arm core has a debug communications channel (dcc) function built-in. the dcc allows a program running on the target to communicate with the host debugger or another separate host without stopping the program ?ow or even entering the debug state. the dcc is accessed as a co-processor 14 by the program running on the arm7tdmi-s core. the dcc allows the jtag port to be used for sending and receiving data without affecting the normal program ?ow. the dcc data and control registers are mapped in to addresses in the embeddedice logic.
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 27 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers the jtag clock (tck) must be slower than 1 6 of the cpu clock (cclk) for the jtag interface to operate. 6.20.2 realmonitor realmonitor is a con?gurable software module, developed by arm inc., which enables real-time debug. it is a lightweight debug monitor that runs in the background while users debug their foreground application. it communicates with the host using the dcc, which is present in the embeddedice logic. the LPC2157/2158 contain a speci?c con?guration of realmonitor software programmed into the on-chip ?ash memory. 6.21 lcd driver 6.21.1 general description the lcd segment driver in the LPC2157/2158 can interface to most lcds using low multiplex rates. it generates the drive signals for static or multiplexed lcds containing up to four backplanes and up to 32 segments. the lcd controller communicates to a host using the i 2 c-bus. the i 2 c-bus clock and data signals for both the microcontroller and the lcd driver are available on the LPC2157/2158 providing system ?exibility. communication overhead to manage the display is minimized by an on-chip display ram with auto-increment addressing, hardware subaddressing, and display memory switching (static and duplex drive modes). please refer to pcf8576d data sheet for electrical data. 6.21.2 functional description the lcd controller is a versatile peripheral device designed to interface microcontrollers to a wide variety of lcds. it can directly drive any static or multiplexed lcd containing up to four backplanes and up to 32 segments. the display con?gurations possible with the lcd controller depend on the number of active backplane outputs required. a selection of display con?gurations is shown in t ab le 4 . all of these con?gurations can be implemented in a typical system. the microcontroller communicates to the lcd controller using the i 2 c-bus.the appropriate biasing voltages for the multiplexed lcd waveforms are generated internally. the only other connections required to complete the system are to the power supplies (v dd(lcd) , v ss and v lcd ) and the lcd panel chosen for the application. 6.21.3 lcd bias voltages lcd biasing voltages are obtained from an internal voltage divider consisting of three series resistors connected between v lcd and v ss . the lcd voltage can be temperature compensated externally via the supply to pin v lcd . a voltage selector drives the multiplexing of the lcd based on programmable con?gurations. table 4. selection of display con?gurations number of 7-segments numeric 14-segments alphanumeric dot matrix backplanes segments digits indicator symbols characters indicator symbols 4 128 16 16 8 16 128 3 9612126 1296 264884864 132442432
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 28 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers 6.21.4 oscillator 6.21.4.1 internal clock an internal oscillator provides the clock signals for the internal logic of the lcd controller and its lcd drive signals. after power-up, pin sda must be high to guarantee that the clock starts. 6.21.5 timing the lcd controller timing controls the internal data ?ow of the device. this includes the transfer of display data from the display ram to the display segment outputs. the timing also generates the lcd frame signal whose frequency is derived from the clock frequency. the frame signal frequency is a ?xed division of the clock frequency from either the internal or an external clock. frame frequency = f osc(ctrl)lcd /24. 6.21.6 display register a display latch holds the display data while the corresponding multiplex signals are generated. there is a one-to-one relationship between the data in the display latch, the lcd segment outputs, and each column of the display ram. 6.21.7 segment outputs the lcd drive section includes 32 segment outputs s0 to s31. the segment output signals are generated according to the multiplexed backplane signals and the display latch data. when less than 32 segment outputs are required, the unused segment outputs should be left open-circuit. 6.21.8 backplane outputs the lcd drive section has four backplane outputs bp0 to bp3. the backplane output signals are generated in accordance with the selected lcd drive mode. if less than four backplane outputs are required, the unused outputs can be left open-circuit. in the 1:3 multiplex drive mode, bp3 carries the same signal as bp1, therefore these two adjacent outputs can be tied together to give enhanced drive capabilities. in the 1:2 multiplex drive mode, bp0 and bp2, bp1 and bp3 respectively carry the same signals and may also be paired to increase the drive capabilities. in the static drive mode the same signal is carried by all four backplane outputs and they can be connected in parallel for very high drive requirements. 6.21.9 display ram the display ram is a static 32 4-bit ram which stores lcd data. there is a one-to-one correspondence between the ram addresses and the segment outputs, and between the individual bits of a ram word and the backplane outputs. the ?rst ram column corresponds to the 32 segments for backplane 0 (bp0). in multiplexed lcd applications the segment data of the second, third and fourth column of the display ram are time-multiplexed with bp1, bp2 and bp3 respectively. 6.21.10 data pointer the display ram is addressed using the data pointer. either a single byte or a series of display bytes may be loaded into any location of the display ram.
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 29 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers 6.21.11 output bank selector the lcd controller includes a ram bank switching feature in the static and 1:2 drive modes. in the static drive mode, the bank select command may request the contents of bit 2 to be selected for display instead of the contents of bit 0. in 1:2 mode, the contents of bits 2 and 3 may be selected instead of bits 0 and 1. this allows display information to be prepared in an alternative bank and then selected for display when it is assembled. 6.21.12 input bank selector the input bank selector loads display data into the display ram based on the selected lcd drive con?guration. the bank select command can be used to load display data in bit 2 in static drive mode or in bits 2 and 3 in 1:2 mode. the input bank selector functions are independent of the output bank selector. 6.21.13 blinker the lcd controller has a very versatile display blinking capability. the whole display can blink at a frequency selected by the blink command. each blink frequency is a multiple integer value of the clock frequency; the ratio between the clock frequency and blink frequency depends on the blink mode selected, as shown in t ab le 5 . an additional feature allows an arbitrary selection of lcd segments to be blinked in the static and 1:2 drive modes. this is implemented without any communication overheads by the output bank selector which alternates the displayed data between the data in the display ram bank and the data in an alternative ram bank at the blink frequency. this mode can also be implemented by the blink command. the entire display can be blinked at a frequency other than the nominal blink frequency by sequentially resetting and setting the display enable bit e at the required rate using the mode set command. blink modes 0.5 hz, 1 hz and 2 hz, and nominal blink frequencies 0.5 hz, 1 hz and 2 hz correspond to an oscillator frequency (f osc(ctrl)lcd ) of 1536 hz at pin clk. the oscillator frequency range is 397 hz to 3046 hz. 6.21.13.1 i 2 c-bus controller the lcd controller acts as an i 2 c-bus slave receiver. in the LPC2157/2158 the hardware subaddress inputs a0, a1 and a2 are tied to v ss setting the hardware subaddress = 0. 6.21.14 input ?lters to enhance noise immunity in electrically adverse environments, rc low-pass ?lters are provided on the sda and scl lines. table 5. blinking frequencies blink mode normal operating mode ratio normal blink frequency off - blinking off 2 hz f osc(ctrl)lcd /768 2 hz 1hz f osc(ctrl)lcd /1536 1 hz 0.5 hz f osc(ctrl)lcd /3072 0.5 hz
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 30 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers 6.21.15 i 2 c-bus slave addresses the i 2 c-bus slave address is 0111 0000. the lcd controller is a write-only device and will not respond to a read access.
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 31 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers 7. limiting values [1] the following applies to the limiting values: a) this product includes circuitry speci?cally designed for the protection of its internal devices from the damaging effects of excessive static charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) parameters are valid over operating temperature range unless otherwise speci?ed. all voltages are with respect to v ss unless otherwise noted. [2] including voltage on outputs in 3-state mode. [3] not to exceed 4.6 v. [4] the peak current is limited to 25 times the corresponding maximum current. [5] dependent on package type. table 6. limiting values in accordance with the absolute maximum rating system (iec 60134). [1] symbol parameter conditions min max unit v dd supply voltage (core and external rail) - 0.5 +3.6 v v dda analog 3.3 v pad supply voltage - 0.5 +4.6 v v i(vbat) input voltage on pin vbat for the rtc - 0.5 +4.6 v v i(vref) input voltage on pin vref - 0.5 +4.6 v v ia analog input voltage on adc related pins - 0.5 +5.1 v v i input voltage 5 v tolerant i/o pins; only valid when the v dd supply voltage is present [2] - 0.5 +6.0 v other i/o pins [2] [3] - 0.5 v dd + 0.5 v i dd supply current per supply pin [4] - 100 ma i ss ground current per ground pin [4] - 100 ma t stg storage temperature [5] - 65 +150 c p tot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption - 1.5 w
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 32 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers 8. static characteristics table 7. static characteristics t amb = - 40 c to +85 c for commercial applications, unless otherwise speci?ed. symbol parameter conditions min typ [1] max unit v dd supply voltage [2] 3.0 3.3 3.6 v v dda analog 3.3 v pad supply voltage 3.0 3.3 3.6 v v i(vbat) input voltage on pin vbat [3] 2.0 3.3 3.6 v v i(vref) input voltage on pin vref 2.5 3.3 v dda v standard port pins, reset, rtck i il low-level input current v i = 0 v; no pull-up - - 3 m a i ih high-level input current v i =v dd ; no pull-down - - 3 m a i oz off-state output current v o =0v; v o =v dd ; no pull-up/down --3 m a i latch i/o latch-up current - (0.5v dd ) < v i < (1.5v dd ); t j < 125 c - - 100 ma v i input voltage pin con?gured to provide a digital function [4] [5] [6] [7] 0 - 5.5 v v o output voltage output active 0 - v dd v v ih high-level input voltage 2.0 - - v v il low-level input voltage - - 0.8 v v hys hysteresis voltage 0.4 - - v v oh high-level output voltage i oh = - 4 ma [8] v dd - 0.4 - - v v ol low-level output voltage i ol = - 4 ma [8] - - 0.4 v i oh high-level output current v oh =v dd - 0.4 v [8] - 4--ma i ol low-level output current v ol = 0.4 v [8] 4--ma i ohs high-level short-circuit output current v oh =0v [9] -- - 45 ma i ols low-level short-circuit output current v ol =v dda [9] --50ma i pd pull-down current v i =5v [10] 10 50 150 m a i pu pull-up current v i =0v [11] - 15 - 50 - 85 m a v dd LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 33 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers i dd(act) active mode supply current v dd = 3.3 v; t amb =25 c; code while(1){} executed from ?ash, no active peripherals cclk = 10 mhz - 1550ma cclk = 60 mhz - 40 70 ma v dd = 3.3 v; t amb =25 c; code executed from ?ash; usb enabled and active; all other peripherals disabled cclk = 12 mhz - 2770ma cclk = 60 mhz - 57 90 ma i dd(pd) power-down mode supply current v dd = 3.3 v; t amb =25 c - 40 100 m a v dd = 3.3 v; t amb =85 c - 250 500 m a i batpd power-down mode battery supply current rtc clock = 32 khz (from rtcx pins); t amb =25 c v dd = 3.0 v; v i(vbat) = 2.5 v [12] -1530 m a v dd = 3.0 v; v i(vbat) = 3.0 v - 20 40 m a i batact active mode battery supply current cclk = 60 mhz; pclk = 15 mhz; pclk enabled to rtck; rtc clock = 32 khz (from rtcx pins); t amb =25 c v dd = 3.0 v; v i(vbat) = 3.0 v [12] -78- m a i batact(opt) optimized active mode battery supply current pclk disabled to rtck in the pconp register; rtc clock = 32 khz (from rtcx pins); t amb =25 c; v i(vbat) = 3.3 v cclk = 25 mhz [12] [13] -23- m a cclk = 60 mhz - 30 - m a i 2 c-bus pins v ih high-level input voltage 0.7v dd --v v il low-level input voltage - - 0.3v dd v v hys hysteresis voltage - 0.5v dd -v v ol low-level output voltage i ols = 3 ma [8] - - 0.4 v i li input leakage current v i =v dd [14] -24 m a v i = 5 v - 10 22 m a oscillator pins v i(xtal1) input voltage on pin xtal1 0 - 1.8 v table 7. static characteristics continued t amb = - 40 c to +85 c for commercial applications, unless otherwise speci?ed. symbol parameter conditions min typ [1] max unit
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 34 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers [1] typical ratings are not guaranteed. the values listed are at room temperature (25 c), nominal supply voltages. [2] core and external rail. [3] the rtc typically fails when v i(vbat) drops below 1.6 v. [4] including voltage on outputs in 3-state mode. [5] v dd supply voltages must be present. [6] 3-state outputs go into 3-state mode when v dd is grounded. [7] please also see the errata note mentioned in errata sheet. [8] accounts for 100 mv voltage drop in all supply lines. [9] allowed as long as the current limit does not exceed the maximum current allowed by the device. [10] minimum condition for v i = 4.5 v, maximum condition for v i = 5.5 v. [11] applies to p1[16] to p1[31]. [12] on pin vbat. [13] optimized for low battery consumption. [14] to v ss . [15] includes external resistors of 18 w 1 % on d+ and d - . v o(xtal2) output voltage on pin xtal2 0 - 1.8 v v i(rtcx1) input voltage on pin rtcx1 0 - 1.8 v v o(rtcx2) output voltage on pin rtcx2 0 - 1.8 v usb pins i oz off-state output current 0v LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 35 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers [1] the adc is monotonic, there are no missing codes. [2] the differential linearity error (e d ) is the difference between the actual step width and the ideal step width. see figure 7 . [3] the integral non-linearity (e l(adj) ) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. see figure 7 . [4] the offset error (e o ) is the absolute difference between the straight line which ?ts the actual curve and the straight line which ?ts the ideal curve. see figure 7 . [5] the gain error (e g ) is the relative difference in percent between the straight line ?tting the actual transfer curve after removing offset error, and the straight line which ?ts the ideal transfer curve. see figure 7 . [6] the absolute error (e t ) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated adc and the ideal transfer curve. see figure 7 . [7] see figure 8 . table 8. adc static characteristics v dda = 2.5 v to 3.6 v; t amb = - 40 c to +85 c unless otherwise speci?ed; adc frequency 4.5 mhz. symbol parameter conditions min typ max unit v ia analog input voltage 0 - v dda v c ia analog input capacitance - - 1 pf e d differential linearity error v ssa =0v, v dda = 3.3 v [1] [2] -- 1 lsb e l(adj) integral non-linearity v ssa =0v, v dda = 3.3 v [3] -- 2 lsb e o offset error v ssa =0v, v dda = 3.3 v [4] -- 3 lsb e g gain error v ssa =0v, v dda = 3.3 v [5] -- 0.5 % e t absolute error v ssa =0v, v dda = 3.3 v [6] -- 4 lsb r vsi voltage source interface resistance [7] --40 k w
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 36 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential linearity error (e d ). (4) integral non-linearity (e l(adj) ). (5) center of a step of the actual transfer curve. fig 7. adc characteristics 002aac046 1023 1022 1021 1020 1019 (2) (1) 1024 1018 1019 1020 1021 1022 1023 7 123456 7 6 5 4 3 2 1 0 1018 (5) (4) (3) 1 lsb (ideal) code out v dda - v ssa 1024 offset error e o gain error e g offset error e o v ia (lsb ideal ) 1 lsb =
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 37 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers fig 8. suggested adc interface - LPC2157/2158 adx[y] pin lpc2xxx adx[y] sample adx[y] 20 k w 3 pf 5 pf r vsi v ss v ext 002aad458
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 38 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers 9. dynamic characteristics [1] characterized but not implemented as production test. guaranteed by design. [1] parameters are valid over operating temperature range unless otherwise speci?ed. [2] typical ratings are not guaranteed. the values listed are at room temperature (25 c), nominal supply voltages. [3] bus capacitance c b in pf, from 10 pf to 400 pf. table 9. dynamic characteristics of usb pins (full-speed) c l = 50 pf; r pu = 1.5 k w on d+ to v dd , unless otherwise speci?ed. symbol parameter conditions min typ max unit t r rise time 10 % to 90 % 4 - 20 ns t f fall time 10 % to 90 % 4 - 20 ns t frfm differential rise and fall time matching (t r /t f ) 90 - 110 % v crs output signal crossover voltage 1.3 - 2.0 v t feopt source se0 interval of eop see figure 10 160 - 175 ns t fdeop source jitter for differential transition to se0 transition see figure 10 - 2 - +5 ns t jr1 receiver jitter to next transition - 18.5 - +18.5 ns t jr2 receiver jitter for paired transitions 10 % to 90 % - 9 - +9 ns t eopr1 eop width at receiver must reject as eop; see figure 10 [1] 40 --ns t eopr2 eop width at receiver must accept as eop; see figure 10 [1] 82 --ns table 10. dynamic characteristics t amb = - 40 c to +85 c for commercial applications, v dd over speci?ed ranges [1] symbol parameter conditions min typ [2] max unit external clock f osc oscillator frequency 10 - 25 mhz t cy(clk) clock cycle time 40 - 100 ns t chcx clock high time t cy(clk) 0.4 - - ns t clcx clock low time t cy(clk) 0.4 - - ns t clch clock rise time - - 5 ns t chcl clock fall time - - 5 ns port pins (p0[2], p0[3], p0[11], and p0[14]) t r(o) output rise time - 10 - ns t f(o) output fall time - 10 - ns i 2 c-bus pins (p0[2], p0[3], p0[11], and p0[14]) t f(o) output fall time v ih to v il 20 + 0.1 c b [3] --ns
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 39 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers 9.1 timing 10. application information 10.1 suggested usb interface solutions fig 9. external clock timing (with an amplitude of at least v i(rms) = 200 mv) t chcl t clcx t chcx t cy(clk) t clch 002aaa907 fig 10. differential data-to-eop transition skew and eop width 002aab561 t period differential data lines crossover point source eop width: t feopt receiver eop width: t eopr1 , t eopr2 crossover point extended differential data to se0/eop skew n t period + t fdeop fig 11. lpc2158 usb interface using the connect function on pin 17 lpc2158 usb-b connector d + connect soft-connect switch d - vbus v ss v dd r1 1.5 k w r s = 33 w 002aad410 r s = 33 w
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 40 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers fig 12. lpc2158 usb interface using the up_led function on pin 17 lpc2158 v dd r1 1.5 k w r2 up_led 002aad411 usb-b connector d + d - vbus v ss r s = 33 w r s = 33 w
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 41 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers 11. package outline fig 13. package outline sot407-1 (lqfp100) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 14.1 13.9 0.5 16.25 15.75 1.15 0.85 7 0 o o 0.08 0.08 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot407-1 136e20 ms-026 00-02-01 03-02-20 d (1) (1) (1) 14.1 13.9 h d 16.25 15.75 e z 1.15 0.85 d b p e q e a 1 a l p detail x l (a ) 3 b 25 c d h b p e h a 2 v m b d z d a z e e v m a x 1 100 76 75 51 50 26 y pin 1 index w m w m 0 5 10 mm scale lqfp100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm sot407-1
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 42 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers 12. abbreviations table 11. abbreviations acronym description adc analog-to-digital converter ahb advanced high-performance bus amba advanced microcontroller bus architecture apb advanced peripheral bus bod brown-out detection dac digital-to-analog converter dcc debug communications channel dma direct memory access fifo first in, first out gpio general purpose input/output i/o input/output isp in-system programming jtag joint test action group mcu microcontroller unit pll phase-locked loop por power-on reset pwm pulse width modulator rc resistance-capacitance spi serial peripheral interface ssi synchronous serial interface ssp synchronous serial port ttl transistor-transistor logic uart universal asynchronous receiver/transmitter
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 43 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers 13. revision history table 12. revision history document id release date data sheet status change notice supersedes LPC2157_2158_2 20090209 product data sheet - LPC2157_2158_1 modi?cations: ? section 2 f eatures : removed rc oscillator feature ? section 2 f eatures : added cpu operating voltage feature ? section 5.2 pin descr iption : description pin 82 p1[29]/tck modi?ed ? section 6.20.1 embeddedice : added jtag clock condition (last paragraph) ? t ab le 7 static char acter istics : v hys , 0.4 v moved from typ to min column ? t ab le 7 static char acter istics : added table note [7] LPC2157_2158_1 20081015 product data sheet - -
LPC2157_2158_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 9 february 2009 44 of 45 nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers 14. legal information 14.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 14.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 14.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 14.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. i 2 c-bus logo is a trademark of nxp b.v. goodlink is a trademark of st-nxp wireless. softconnect is a trademark of st-nxp wireless. 15. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
nxp semiconductors LPC2157/2158 single-chip 16-bit/32-bit microcontrollers ? nxp b.v. 2009. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 9 february 2009 document identifier: LPC2157_2158_2 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 16. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 functional description . . . . . . . . . . . . . . . . . . 15 6.1 architectural overview. . . . . . . . . . . . . . . . . . . 15 6.2 on-chip ?ash program memory . . . . . . . . . . . 15 6.3 on-chip static ram. . . . . . . . . . . . . . . . . . . . . 15 6.4 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.5 interrupt controller . . . . . . . . . . . . . . . . . . . . . 16 6.5.1 interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 17 6.6 pin connect block . . . . . . . . . . . . . . . . . . . . . . 17 6.7 fast general purpose parallel i/o . . . . . . . . . . 17 6.7.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.8 10-bit adc . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.8.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.9 10-bit dac . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.9.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.10 usb 2.0 device controller (lpc2158 only) . . . 18 6.10.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.11 uarts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.11.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.12 i 2 c-bus serial i/o controller . . . . . . . . . . . . . . 20 6.12.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.13 spi serial i/o controller. . . . . . . . . . . . . . . . . . 20 6.13.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.14 ssp serial i/o controller . . . . . . . . . . . . . . . . . 20 6.14.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.15 general purpose timers/external event counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.15.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.16 watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 22 6.16.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.17 real-time clock . . . . . . . . . . . . . . . . . . . . . . . . 22 6.17.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.18 pulse width modulator . . . . . . . . . . . . . . . . . . 22 6.18.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.19 system control . . . . . . . . . . . . . . . . . . . . . . . . 24 6.19.1 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . 24 6.19.2 pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.19.3 reset and wake-up timer . . . . . . . . . . . . . . . . 24 6.19.4 brownout detector. . . . . . . . . . . . . . . . . . . . . . 25 6.19.5 code security . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.19.6 external interrupt inputs . . . . . . . . . . . . . . . . . 25 6.19.7 memory mapping control . . . . . . . . . . . . . . . . 25 6.19.8 power control . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.19.9 apb bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.20 emulation and debugging. . . . . . . . . . . . . . . . 26 6.20.1 embeddedice . . . . . . . . . . . . . . . . . . . . . . . . 26 6.20.2 realmonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.21 lcd driver . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.21.1 general description . . . . . . . . . . . . . . . . . . . . 27 6.21.2 functional description . . . . . . . . . . . . . . . . . . 27 6.21.3 lcd bias voltages . . . . . . . . . . . . . . . . . . . . . 27 6.21.4 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.21.4.1 internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.21.5 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.21.6 display register. . . . . . . . . . . . . . . . . . . . . . . . 28 6.21.7 segment outputs . . . . . . . . . . . . . . . . . . . . . . 28 6.21.8 backplane outputs . . . . . . . . . . . . . . . . . . . . . 28 6.21.9 display ram. . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.21.10 data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.21.11 output bank selector . . . . . . . . . . . . . . . . . . . 29 6.21.12 input bank selector. . . . . . . . . . . . . . . . . . . . . 29 6.21.13 blinker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.21.13.1 i 2 c-bus controller . . . . . . . . . . . . . . . . . . . . . . 29 6.21.14 input ?lters . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.21.15 i 2 c-bus slave addresses . . . . . . . . . . . . . . . . 30 7 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 31 8 static characteristics . . . . . . . . . . . . . . . . . . . 32 9 dynamic characteristics . . . . . . . . . . . . . . . . . 38 9.1 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10 application information . . . . . . . . . . . . . . . . . 39 10.1 suggested usb interface solutions . . . . . . . . 39 11 package outline . . . . . . . . . . . . . . . . . . . . . . . . 41 12 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 42 13 revision history . . . . . . . . . . . . . . . . . . . . . . . 43 14 legal information . . . . . . . . . . . . . . . . . . . . . . 44 14.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 44 14.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 14.3 disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 44 14.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 44 15 contact information . . . . . . . . . . . . . . . . . . . . 44 16 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

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